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Yasunaga Moritoshi

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  • FPGAを用いたk-means法の高速化とチップマウンタへの応用
    中村匠吾; 安永 守利; 金澤健治; 相部範之; 江原宏紀
    電子情報通信学会技術研究報告(リコンフィギャラブルシステム研究会), 2017-09
  • 適応的に信号品質を改善できる超高速伝送線の一検討
    安永 守利
    電子情報通信学会第64回 機能集積情報システム研究会,信学技報 (FIIS2017)/(No. 462), 2017-10
  • 遺伝的アルゴリズムを用いた高信号品質配線設計とその解析
    松岡駿平; 安永 守利
    電子情報通信学会第63回 機能集積情報システム研究会,信学技報 (FIIS2017)/(No. 452), 2017-06
  • Development of Technology to Improve Hammering Test
    歌川紀之; 安永 守利; 杉本恒美
    Concrete Journal/55(6)/pp.502-509, 2017-06
  • An impact-echo method using self-organizing map
    Shimada Takumu; Komatsu Hiroto; Kawahara Yuuki; Utagawa N...
    Proc. The 23th Int’l Symp. on Artificial Life and Robotics 2018 (AROB 23th’18)/pp.490-493, 2018-01
  • Hardware implementation of a self-organizing map using a zynq FPGA and its application to impact-echo testing
    Komatsu Hiroto; Kawahara Yuuki; Shimada Takumu; Utagawa N...
    Proc. The 23th Int’l Symp. on Artificial Life and Robotics 2018 (AROB 23th’18)/pp.494-497, 2018-01
  • High Signal Integrity Design for Transmission System Including High-Parasitic Inductance Connectors
    Matsuoka Shumpei; Akutsu Shun; Yasunaga Moritoshi
    IEEE CPMT Symposium Japan 2017/pp.133-134, 2017-11
  • Waveform Learning Based on a Genetic Algorithm and Its Application to Signal Integrity Improvement
    Yasunaga Moritoshi; Yoshihara Ikuo
    IEEE International Conference on Soft Computing and Machine Intelligence (ISCMI 2017)/pp.145-148, 2017-11
  • An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search
    Sassa Shohei; Kanazawa Kenji; Cai Shaowei; Yasunaga Morit...
    ACM SIGARCH Computer Architecture News 44(4), pp.33-37 (Post Proceedings of 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2016)/pp.33-37, 2016-07
  • Signal Integrity Improvement Design of Lossy Transmission Line Based on a Single-shot Pulse
    Yokoshima Naoki; Yasunaga Moritoshi
    Proceedings of 2016 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2016)/pp.149-151, 2016-12
  • A High Signal Integrity Interconnect Design Using a Genetic Algorithm and Its Solution Analysis
    Matsuoka Shumpei; Yasunaga Moritoshi
    Proceedings of 2016 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2016)/pp.185-187, 2016-12
  • A High Signal Integrity Design Based on Machine Learning
    Yasunaga Moritoshi
    Proceedings of JIEP Annual Meeting/31/pp.283-286, 2017-03
  • Evolutionary Design of High Signal Integrity Interconnection Based on Eye-diagram
    Odaira Tetsuya; Yokoshima Naoki; Yoshihara Ikuo; Yoshihar...
    Proc. International Symposium on Artificial Life and Robotics 2017 (AROB 22th '17), 2017-01
  • FPGAを用いた画像処理応用のためのMonotone Chain アルゴリズムの高速計算
    監物 香保里; 金澤 健治; 森 大和; 相部 範之; 安永 守利
    電子情報通信学会論文誌/J100-D(1)/pp.1-13, 2017-01
  • A Passive Equalizer and Its Design Methodology for Global Interconnects in VLSIs
    Yasunaga Moritoshi; Yokoshima Naoki; Yoshihara Ikuo
  • An evolutionary design methodology of printed circuit boards for high-speed VLSIs
    Yasunaga Moritoshi; Yoshihara Ikuo
    Artificial Life and Robotics/21(2)/pp.171-176, 2016-06
  • An Evolutionary Design Methodology for High Speed Point-to-Point Transmission Line Used in Printed Circuit Boards
    Akutsu Syun; Yasunaga Moritoshi
    Proc. The 21th Int’l Symp. on Artificial Life and Robotics 2016 (AROB 20th’16)/pp.317-321, 2016-01
  • Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines -Towards Realization of Branched Traces for High-Speed Data Transfer in PCBs
    Yasunaga Moritoshi; Kuribara Yusuke; Inoue Hirofumi; Yosh...
    IEEE Symposium Series on Computational Intelligence 2015/ International Conference on Evolvable Systems 2015/pp.1236-1243, 2015-12
  • Bio-inspired Design of High-speed Transmission Line -High Signal Integrity Design for Printed Circuit Board Traces in GHz Domain
    Yasunaga Moritoshi
    Fourth International Conference on Intelligent Systems and Applications (INTELLI )2015/pp.23-25, 2015-10
  • High-Speed Calculation of Convex Hull in 2D Images Using FPGA
    Yasunaga Moritoshi
    Symposyum on Parallel Computing with FPGAs 2015/pp.533-542, 2015-09
  • Segmental Transmission Line: Its Practical Application The Optimized PCB Trace Design Using a Genetic Algorithm
    Yasunaga Moritoshi; Shimada Hiroki; Seki Katsuyuki; Yoshi...
    IEEE Proceedings of Symposium Series on Computational Intelligence 2014/ International Conference on Evolvable Systems 2014/pp.23-30, 2014-12
  • A-9-1 A Measurement Method for the Range of Simultaneous Soft Errors
    益田 昇; 安永 守利
    Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference/2015/p.105, 2015-08
  • Special Section on Optimization and Learning Algorithms of Small Embedded Devices and Related Software/Hardware Implementation FOREWORD
    Yasunaga Moritoshi
    YASUNAGA Moritoshi
    IEICE Trans. Inf. & Syst./98(9)/pp.1621-1621, 2015
  • Feature Extraction from Non-transcribed Region of Dictyostelium Discoideum using Moire Picture
    Yoshihara Ikuo; Onitani Toshiro; Yamamori Kunihito; Yasun...
    Memoirs of the Faculty of Engineering, Miyazaki University/32/pp.271-276, 2003-07