BOKU Taisuke
- Articles
- A Scalar Architecture for Pseudo Vector Processing based on Slide-Windowed Registers
H. Nakamura; H. Imori; K. Nakazawa; T. Boku; I. Nakata; Y...
Proc. of ICS'93, Tokyo/p.298-307, 1993-01 - スライドウィンドウ方式による擬似ベクトルプロセッサ
位守 弘充; 中村 宏; 朴 泰祐; 中澤 喜三郎
情報処理学会論文誌/34(12), 1993-01 - Superscalar Processor Design with Hardware Description Language AIDL
H. Morimoto; K. Yamazaki; H. Nakamura; T. Boku; and K. N...
Proc. of 2nd Asia Pacific Conf. on Hardware Description Language, Nagoya/p.51-58, 1994-01 - Pseudo Vector Processor for High-speed List Vector Computation with Hiding Memory Access Latency
Proc. of IEEE TENCON'94; Singapore; +朴 泰祐
*EMPTY*/p.338-342, 1994-01 - Evaluation of Pseudo Vector Processor based on Slide-Windowed Registers
H. Nakamura; K. Nakazawa; H. Li; H. Imori; T. Boku; I. N...
Proc. of HICSS'94, Honolulu/p.368-377, 1994-01 - Preliminary evaluation of NAS Parallel Benchmarks on CP-PACS
K. Itakura; M. Hattori; T. Boku; H. Nakamura; and K. Nak...
Proc. of PERMEAN'95, Beppu/p.68-77, 1995-01 - INSPIRE : A general purpose network simulator generating system for massively parallel processors
T. Boku; T. Harada; T. Sone; H. Nakamura; and K. Nakazawa
Proc. of PERMEAN'95, Beppu/p.24-33, 1995-01 - ハイパクロスバ・ネットワークにおける転送性能向上のための手法とその評価
朴 泰祐; 板倉 憲一; 曽根 猛; 三島健; 中澤 喜三郎; 中村 宏
情報処理学会論文誌/36(7)/p.1610-1618, 1995-01 - ハイパクロスバ網における適応ルーチングの導入とその評価
朴 泰祐; 曽根 猛; 三島 健; 板倉 憲一; 中村 宏; 中澤 喜三郎
電子情報通信学会論文誌/J78-D-I(2)/p.108-117, 1995-01 - The MDX (Multi-Dimensional X'bar): A class of networks for large scale multiprocessors
A. Murata; T. Boku; T. Harada; H. Amano
Proc. of PDCS'96/p.296-303, 1996-01 - VIPPES: A performance pre-evaluation system for parallel processors
T. Boku; M. Mishima; K. Itakura; H. Nakamura; K. Nakazawa
Proc. of HPCN'96, Brussel, 1996-01 - 擬似ベクトルプロセッサにおける高速リストベクトル処理
廣野哲; 中村宏; 朴泰祐; 中澤喜三郎
情報処理学会論文誌/37(10)/p.1850-1858, 1996-01 - ハイパクロスバ・ネットワークにおけるVirtual Channelの動的選択による適応ルーティング
曽根 猛; 朴 泰祐; 中村 宏; 中澤 喜三郎
情報処理学会論文誌/37(7)/p.1409-1418, 1996-01 - The MDX (Multi-Dimensional X'bar): A Class of Networks for Large Scale Multiprocessors
A. Murata; T. Boku; and H. Amano
IEICE Trans. on Information and Systems/E79-D(8), 1996-01 - Effectiveness of Register Preloading on CP-PACS Node Processor
H. Nakamura; K. Itakura; M. Matsubara; T. Boku; K. Nakazawa
Proc. of Innovative Architecture for Future Generation High-Performance Processors and Systems, Mauii/p.83-90, 1997-01 - CP-PACS: A massively parallel processor for large scale scientific calculations
T. Boku; K. Itakura; H. Nakamura; K. Nakazawa
Proc. of ICS'97/p.108-115, 1997-01 - Performance evaluation of CP-PACS on CG benchmark
K. Itakura; T. Boku; H. Nakamura; K. Nakazawa
Proc. of HPCAsia'97, Seoul/p.678-683, 1997-01 - Performance Improvement for Matrix Calculation on CP-PACS Node Processor
Y. Abei; K. Itakura; T. Boku; H. Nakamura; K. Nakazaw
Proc. of HPCAsia'97, Seoul/p.672-677, 1997-01 - The Architecture of Massively Parallel Processor CP-PACS
T. Boku; H. Nakamura; K. Nakazawa; Y. Iwasaki
Proc. of 2nd pAs, Aizu/p.31-40, 1997-01 - Advanced Processor Design Using Hardware Description Language AIDL
T. Morimoto; K. Saito; H. Nakamura; T. Boku; K. Nakazawa
Proc. of Asia and South Pacific Design Automation Conference 1997, Makuhari/p.387-390, 1997-01 - VIPPES : A Virtual Parallel Processing System Simulation Environment
T. Boku; M. Mishima; K. Itakura
Proc. of HPCAsia'98, Singapore/p.843-853, 1998-01 - Large Scale Molecular Dynamics Simulations on CP-PACS
M. Matsubara; K. Itakura; T. Boku
Proc. of HPCAsia'98, Singapore/p.321-331, 1998-01 - Accuracy of fast performance prediction by instrumentation tool EXCIT
K. Kubota; M. Sato; K. Itakura; T. Boku
Proc. of HPCAsia'98, Singapore/p.1031-1038, 1998-01 - Practical Simulation of Large-Scale Parallel Programs and Its Performance Analysis of the NAS Parallel Bechmarks
K. Kutoba; K. Itakura; M. Sato; T. Boku
Proc. of Euro-Par'98, Manchester/LNCS(1470)/p.244-254, 1998-01 - 超並列計算機CP-PACSにおけるNPB Kernel CGの評価
板倉憲一; 松原正純; 朴泰祐; 中村宏; 中澤喜三郎
情報処理学会論文誌/39(6)/p.1757-1765, 1998-01 - more...
- A Scalar Architecture for Pseudo Vector Processing based on Slide-Windowed Registers