Kobayashi Ryohei
- Refereed academic journal/Refereed international conference paper
- OpenCL-enabled GPU-FPGA Accelerated Computing with Inter-FPGA Communication
Kobayashi Ryohei; Fujita Norihisa; Yamaguchi Yoshiki; Nak...
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region Workshops/pp.17-20, 2020-01 - GPU-FPGA Heterogeneous Computing with OpenCL-Enabled Direct Memory Access
Kobayashi Ryohei; Fujita Norihisa; Yamaguchi Yoshiki; Nak...
2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)/pp.489-498, 2019-07 - Parallel Processing on FPGA Combining Computation and Communication in OpenCL Programming
Fujita Norihisa; Kobayashi Ryohei; Yamaguchi Yoshiki; Bok...
2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)/pp.479-488, 2019-07 - Optimization on Astrophysical Radiative Transfer Code for FPGAs with OpenCL
藤田 典久; 小林 諒平; 山口 佳樹; 朴 泰祐; 吉川 耕司; 安部 牧人; 梅村 雅之
IPSJ Transactions on Advanced Computing System/12(3)/pp.64-75, 2019-07 - OpenCL-enabled high performance direct memory access for GPU-FPGA cooperative computation
Kobayashi Ryohei; Fujita Norihisa; Yamaguchi Yoshiki; Bok...
Proceedings of the HPC Asia 2019 Workshops/pp.6-9, 2019-01 - Accelerating Space Radiative Transfer on FPGA using OpenCL
Fujita Norihisa; Kobayashi Ryohei; Yamaguchi Yoshiki; Oob...
HEART 2018 Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies Article No. 6/pp.6:1-6:7, 2018-06 - ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment
SATO Shimpei; KOBAYASHI Ryohei; KISE Kenji
IEICE Transactions on Information and Systems/E101D(2)/pp.344-353, 2018-02 - OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing
Kobayashi Ryohei; Oobata Yuma; Fujita Norihisa; Yamaguchi...
HPC Asia 2018 Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region/pp.192-201, 2018-01 - A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism
Kobayashi Ryohei; Kise Kenji
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS/E100D(5)/pp.1003-1015, 2017-05 - A High-speed Verilog HDL Simulation Method using a Lightweight Translator
Kobayashi Ryohei; Misono Tomohiro; Kise Kenji
ACM SIGARCH Computer Architecture News - HEART '16/44(4)/pp.26-31, 2016-09 - Effective Parallel Simulation of ArchHDL under Manycore Environment
Misono Tomohiro; Kobayashi Ryohei; Kise Kenji
2015 Third International Symposium on Computing and Networking (CANDAR)/pp.140-146, 2015-12 - FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems
Kobayashi Ryohei; Kise Kenji
2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip/pp.49-56, 2015-09 - Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research
Ogawa Eri; Matsuda Yuki; Misono Tomohiro; Kobayashi Ryoh...
2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip/pp.65-72, 2015-09 - Scalable Stencil-computation Accelerator by Employing Multiple Small FPGAs
小林 諒平; 吉瀬 謙二
IPSJ Transactions on Advanced Computing System/6(4)/pp.1-13, 2013-10 - Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations
Kobayashi Ryohei; Takamaeda-Yamazaki Shinya; Kise Kenji
2012 Third International Conference on Networking and Computing/pp.343-349, 2012-12
- OpenCL-enabled GPU-FPGA Accelerated Computing with Inter-FPGA Communication