KOJIMA Takuya
- Articles
- SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks
Kojima Takuya; Yanai Yosuke; Okuhara Hayate; Amano Hi...
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 27), 2024-04 - CGRA architecture generation for implementing a systolic array
Hajime Takishita; 小島 拓也; Hideharu Amano
ASPIRE Worhshop, 2024-03 - A Data-Flow Visualization for CGRA Debugging
Saito Makoto; Kojima Takuya; Takase Hideki; Nakamura ...
ASPIRE Workshop, 2024-03 - A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops
Kamei Aika; Amano Hideharu; Kojima Takuya; Yokoyama D...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems/31(4)/pp.532-542, 2023-1-30 - A Scalable Body Bias Optimization Method Towards Low-Power CGRAs
Kojima Takuya; Okuhara Hayate; Kondo Masaaki; Amano H...
IEEE Micro/43(1)/pp.49-57, 2023-01 - Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning
Kojima Takuya; Ohwada Ayaka; Amano Hideharu
IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS)/33(5)/pp.1213-1230, 2022-05 - Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures
IKEZOE Takeharu; KOJIMA Takuya; AMANO Hideharu
IEICE Transactions on Electronics/E104.C(6)/pp.215-225, 2021-06-01 - CubeSim: A Cycle Accurate Simulator for Multicore System with 3D SiP
小島 拓也; 池添 赳治; 天野 英晴
電子情報通信学会論文誌D 情報・システム/J104-D(4)/pp.228-241, 2021-04-01 - GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse Grained Reconfigurable Architectures
Kojima Takuya; Doan Nguyen Anh Vu; Amano Hideharu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems/28(11)/pp.2383-2396, 2020-11 - A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures
KOJIMA Takuya; AMANO Hideharu
IEICE Transactions on Information and Systems/E102.D(7)/pp.1247-1256, 2019-07-01 - Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures
KOJIMA Takuya; ANDO Naoki; OKUHARA Hayate; DOAN Ng. A...
IEICE Transactions on Information and Systems/E101.D(6)/pp.1532-1540, 2018-06-01
- SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks