小林 諒平(コバヤシ リョウヘイ)
- 査読付き学術雑誌・国際会議論文
- A High-speed Verilog HDL Simulation Method using a Lightweight Translator
Kobayashi Ryohei; Misono Tomohiro; Kise Kenji
ACM SIGARCH Computer Architecture News - HEART '16/44(4)/pp.26-31, 2016-09 - Effective Parallel Simulation of ArchHDL under Manycore Environment
Misono Tomohiro; Kobayashi Ryohei; Kise Kenji
2015 Third International Symposium on Computing and Networking (CANDAR)/pp.140-146, 2015-12 - FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core Systems
Kobayashi Ryohei; Kise Kenji
2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip/pp.49-56, 2015-09 - Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and Research
Ogawa Eri; Matsuda Yuki; Misono Tomohiro; Kobayashi Ryoh...
2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip/pp.65-72, 2015-09 - 多数の小容量FPGAを用いたスケーラブルなステンシル計算機
小林 諒平; 吉瀬 謙二
情報処理学会論文誌コンピューティングシステム（ACS）/6(4)/pp.1-13, 2013-10 - Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations
Kobayashi Ryohei; Takamaeda-Yamazaki Shinya; Kise Kenji
2012 Third International Conference on Networking and Computing/pp.343-349, 2012-12
- A High-speed Verilog HDL Simulation Method using a Lightweight Translator